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Micron sets 2027 start for bonded 400-layer NAND

The company will use wafer bonding to double storage density to 42 Gb/mm2.

By Imani Donovan ·

Illustration for: Micron sets 2027 start for bonded 400-layer NAND
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Micron Technology plans to begin production of its G11 3D NAND flash in the second half of 2027. The company presented the roadmap during an event this week, stating that the new generation will double storage density while improving speed and efficiency.

The new chips will store approximately 42 gigabits per square millimeter in triple-level-cell mode. This represents a doubling from the current G9 generation, which operates at about 21 gigabits per square millimeter. Micron projects that input/output speeds will rise by up to 50 percent, reaching 5,400 MT/s from the current 3,600 MT/s. Power consumption for transferring each bit should drop by more than 25 percent.

The design relies on wafer-on-wafer bonding, a method already employed by Chinese competitor YMTC. This process allows Micron to manufacture the memory array and peripheral circuitry on separate wafers. The company then bonds these wafers together, enabling independent optimization of the logic and memory components. Scott DeBoer, Micron's president and chief technology and products officer, described the timing as appropriate for the technology. He labeled G11 the world's most advanced NAND.

G11 will exceed 400 layers, though Micron has not disclosed the exact count of active wordlines or memory decks. The density increase comes from a combination of additional layers and a smaller memory cell pitch. The company intends to release further technical specifications in 2027, closer to the start of high-volume production. The new architecture targets conventional solid-state drives for client and data center markets, as well as storage devices designed for artificial intelligence workloads.

Micron stated that it will continue scaling in three dimensions rather than relying solely on layer counts. The company is developing high-mobility materials and ultra-dense cell architectures to improve transistor characteristics and reduce energy use. DeBoer noted that the firm has a strong roadmap beyond G11, focusing on new materials and denser cell structures. He emphasized that both the industry and Micron are scaling by adding layers and shrinking cell dimensions.

Micron has not released architectural details or production schedules for generations following G11. The company expects to share more information as high-volume production approaches. Demand for NAND-based storage remains strong, and the race for higher layer counts is expected to continue in the coming years.

Source: Tom's Hardware

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